This invention relates to integrated-circuit memory arrays, including electrically-programmable, read-only-memory (EPROM) arrays, and to circuitry and methodology for discharging charged column lines of such arrays.
An EPROM array is one example of an integrated circuit in which the circuit and method of this invention may be used. EPROM arrays include floating-gate memory cells arranged in rows and columns. The floating gate of a programmed memory cell is charged with electrons, and the electrons in turn render the source-drain path under the charged floating gate nonconductive when a chosen row-line select voltage is applied to the control gate. The nonconductive state is read as a "zero" bit. The floating gate of a non-programmed cell is neutrally charged such that the source-drain path under the non-programmed floating gate is conductive when the same chosen row-line select voltage is applied to the control gate. The conductive state is read as a "one" bit.
Each column and row of an EPROM array may contain thousands of cells. The sources of each cell in a column are connected to a virtual-ground line (source-column line). The drains of each cell in a column are connected to a separate bitline (drain-column line). The control gates of each cell in a row are connected to a wordline.
During cell programming, appropriate programming voltages are applied to the selected control-gate wordline and the selected source-column line to create a high-current condition in the selected channel region, injecting channel-hot electrons and/or avalanche-breakdown electrons across the channel oxide to the floating gate. The relatively high programming voltage applied to the selected drain-column line must be removed from the selected drain-column line after programming and prior to reading the selected cell to verify the programmed state. The removal of the voltage should be accomplished rapidly to minimize programming time. However, if sufficient time is not allowed for removal of the voltage, an improperly programmed memory cell will be erroneously detected as a "zero".
In virtual-ground-type arrays, the drain-column discharge problem is made more difficult because the size of the drain-column-line capacitance depends on the column selected and on the previously defined data pattern. Since a virtual-ground-type array is a series combination of N-type enhancement memory cells having common control gates, all of the drain-column lines and source-column lines (sometimes referred to as virtual-ground lines) emanating from a drain-column line driven to high voltage may themselves be charged to high voltage via the series connections. As the number of charged drain-column lines and/or source column lines increases, the amount of charge, and the time to discharge that charge, increases.
U.S. Pat. No. 4,797,857 describes a discharge method for an equalized biased array. The method disclosed in that Patent involves use of a large static N-channel transistor load to discharge the array through drain-column-line transistor loads and source-column-line N-channel transistor loads. A circuit detects when the array is discharged, then turns off the large discharge transistor. The method disclosed in that Patent cannot be used with bias circuitry such as that described in co-pending U.S. Pat. No. 5,132,933. The bias circuitry described in that Patent biases only the drain-column line connected to the sense amplifier and the source-column line connected to the cell that shares the same drain-column line and the same word line as the cell. Individual loads are not connected to each drain-column line and/or source-column line and, therefore, an alternate discharge path is required.
Where such individual loads are not present, there is a need for a circuit and method to remove drain-column programming voltages from selected drain-column lines rapidly in order to minimize programming and verification times and to minimize errors in verification reading.